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1 | 1 | //! SPI bus sharing mechanisms. |
2 | 2 |
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3 | 3 | use embedded_hal::delay::DelayNs; |
4 | | -use embedded_hal::digital::OutputPin; |
| 4 | +use embedded_hal::digital::{NoPin, OutputPin}; |
5 | 5 | use embedded_hal::spi::{ErrorType, Operation, SpiBus, SpiDevice}; |
6 | 6 | #[cfg(feature = "async")] |
7 | 7 | use embedded_hal_async::{ |
@@ -49,6 +49,15 @@ impl<BUS, CS, D> ExclusiveDevice<BUS, CS, D> { |
49 | 49 | } |
50 | 50 | } |
51 | 51 |
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| 52 | +use unwrap_infallible::UnwrapInfallible; |
| 53 | + |
| 54 | +impl<BUS, D> ExclusiveDevice<BUS, NoPin, D> { |
| 55 | + /// Create a new [`ExclusiveDevice`] without a Chip Select (CS) pin. |
| 56 | + pub fn new_no_cs(bus: BUS, delay: D) -> Self { |
| 57 | + ExclusiveDevice::new(bus, NoPin, delay).unwrap_infallible() |
| 58 | + } |
| 59 | +} |
| 60 | + |
52 | 61 | impl<BUS, CS> ExclusiveDevice<BUS, CS, super::NoDelay> { |
53 | 62 | /// Create a new [`ExclusiveDevice`] without support for in-transaction delays. |
54 | 63 | /// |
@@ -83,6 +92,13 @@ impl<BUS, CS> ExclusiveDevice<BUS, CS, super::NoDelay> { |
83 | 92 | } |
84 | 93 | } |
85 | 94 |
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| 95 | +impl<BUS> ExclusiveDevice<BUS, NoPin, super::NoDelay> { |
| 96 | + /// Create a new [`ExclusiveDevice`] without a Chip Select (CS) pin. |
| 97 | + pub fn new_no_cs_no_delay(bus: BUS) -> Self { |
| 98 | + ExclusiveDevice::new_no_delay(bus, NoPin).unwrap_infallible() |
| 99 | + } |
| 100 | +} |
| 101 | + |
86 | 102 | impl<BUS, CS, D> ErrorType for ExclusiveDevice<BUS, CS, D> |
87 | 103 | where |
88 | 104 | BUS: ErrorType, |
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