From a7bdf4905d458b1927b97fa12ede9caf4cf5786b Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Thu, 5 Mar 2026 17:46:17 +0200 Subject: [PATCH] ASoC: SOF: Intel: hda: follow strict BDLE address alignment for ACE4 Intel ACE4 based products require host to strictly follow HDA spec guidance on BDLE address alignment. Each BDLE address must be aligned to 128 bytes, and given ALSA periods are directly mapped to BDLEs, period size must be 128 aligned as well. Reported-by: Peter Ujfalusi Signed-off-by: Kai Vehmanen --- sound/soc/sof/intel/hda-pcm.c | 10 ++++++++-- sound/soc/sof/intel/hda.h | 3 +++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/sound/soc/sof/intel/hda-pcm.c b/sound/soc/sof/intel/hda-pcm.c index da6c1e7263cde1..91b809e41cebfc 100644 --- a/sound/soc/sof/intel/hda-pcm.c +++ b/sound/soc/sof/intel/hda-pcm.c @@ -219,6 +219,7 @@ EXPORT_SYMBOL_NS(hda_dsp_pcm_pointer, "SND_SOC_SOF_INTEL_HDA_COMMON"); int hda_dsp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream) { + const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata); struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct snd_soc_component *scomp = sdev->component; @@ -268,8 +269,13 @@ int hda_dsp_pcm_open(struct snd_sof_dev *sdev, return -ENODEV; } - /* minimum as per HDA spec */ - snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4); + if (chip_info->hw_ip_version >= SOF_INTEL_ACE_4_0) + snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, + SOF_HDA_BDLE_ADDRESS_ALIGNMENT); + else + /* minimum as per HDA spec */ + snd_pcm_hw_constraint_step(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4); /* avoid circular buffer wrap in middle of period */ snd_pcm_hw_constraint_integer(substream->runtime, diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h index 3f0966477ace21..1f571b27803cee 100644 --- a/sound/soc/sof/intel/hda.h +++ b/sound/soc/sof/intel/hda.h @@ -139,6 +139,9 @@ /* SDxFIFOS FIFOS */ #define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0) +/* HDA BDLE size constraints */ +#define SOF_HDA_BDLE_ADDRESS_ALIGNMENT 128 + /* CL: Software Position Based FIFO Capability Registers */ #define SOF_DSP_REG_CL_SPBFIFO \ (SOF_HDA_ADSP_LOADER_BASE + 0x20)