adding support for new MCU (Infineon PSOC-6) along with new board (PSOC-6 AI Kit)

[fjrdev]

Contribution description

This PR adds support for a new board (Infineon PSoC 6 AI Kit) as well as for the MCU (PSOC-62) to RIOT.

The contribution includes:

• a new board definition under boards/infineon-cy8ckit-062s2-ai
• MCU base support for the psoc6 family under cpu/psoc6
• implementations for the basic peripherals
• PSoC 6 specific BLE transport code for using the external on-board CYW43439 controller with NimBLE host
• a BMI270 driver integration under drivers/bmi270
• test applications for the external CYW43439 BLE controller and the BMI270 IMU under tests/drivers/

The PSoC 6 is a dual-core MCU. The device contains a Cortex-M0+ core and a Cortex-M4 core. In the RIOT setup used here, the Cortex-M0+ is used as the boot core and immediately starts the Cortex-M4 application core, which is the core used to run RIOT applications. This is also reflected in the build and flashing flow, where the M0+ boot image and the M4 application image are handled separately. Required features in the Makefile and the main functions therefore are only build for the M4 and separated from the CM0+ by macros.

In addition, the board flashing setup was integrated via OpenOCD using a board-specific configuration file. This target requires the Infineon / ModusToolbox OpenOCD build, because the stock OpenOCD versions commonly shipped by Linux distributions do not provide the PSoC-specific target and flash support needed for this board. To make flashing easier without hardcoding host-local tool paths, the board support adds the MTB_OPENOCD_BASE option, which allows users to point RIOT to their local ModusToolbox OpenOCD installation.

Testing procedure

The port was tested on the infineon-cy8ckit-062s2-ai board for both basic peripheral bring-up and board-specific device integration.

The following applications / tests were built successfully for the Cortex-M4 core:

• examples/basic/hello-world to validate UART
• examples/basic/blinky to validate GPIO
• tests/drivers/bmi270 to validate I2C support together with BMI720 IMU initialization and sensor access
• tests/drivers/cyw43439 to validate external CYW43439 BLE controller integration via UART H4 transport and NimBLE host

The tested procedure for dual-core support is:

• build the Cortex-M4 application image
• build the Cortex-M0+ launcher image
• merge both generated .hex files into a single dual_flash.hex with srec_cat
• flash the merged image via the M0+ target

For example:

make clean
make BOARD=infineon-cy8ckit-062s2-ai CPU_CORE=cortex-m4f
cp bin/infineon-cy8ckit-062s2-ai/<app>.hex /tmp/cm4.hex

make clean
make BOARD=infineon-cy8ckit-062s2-ai CPU_CORE=cortex-m0plus
cp bin/infineon-cy8ckit-062s2-ai/<app>.hex /tmp/cm0.hex

srec_cat /tmp/cm0.hex -Intel /tmp/cm4.hex -Intel -o /tmp/dual_flash.hex -Intel

make flash BOARD=infineon-cy8ckit-062s2-ai CPU_CORE=cortex-m0plus \
     MTB_OPENOCD_BASE=/opt/Tools/ModusToolboxProgtools-1.6/openocd \
     FLASHFILE=/tmp/dual_flash.hex

However, its also possible to only build for the Cortex M0+. This is done by not enabling the Cortex M4 in the cpu_init() and by expanding the ROM/RAM regions of the Cortex M0+ in cpu/psoc6/Makefile.include.

Issues/PRs references

This port was creating along with the MCU porting guide of #22173 .

Declaration of AI-Tools / LLMs usage:

AI-Tools / LLMs that were used are:

• none

[crasbe]

I think it would be good if you could split out the BMI270 driver as a separate PR too. Also this still includes the guide, which is already covered by #22173.

[riot-ci]

Murdock results

❌ FAILED

32e8748 removed bmi270 driver for new PR

Success	Failures	Total	Runtime
5082	0	10520	07m:00s

Artifacts

[crasbe]

Sorry, hit the wrong button 👀

Let me know once you want a (preliminary) review. This is still marked as Draft, so it's WIP I guess?

[fjrdev]

Sorry, hit the wrong button 👀

Let me know once you want a (preliminary) review. This is still marked as Draft, so it's WIP I guess?

Will do, thank you! Yes, this is WIP currently, although I’m unsure how much time I’ll have to continue working on this..