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cpu/stm32u5: Fix LSI initialization#22239

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flxmls wants to merge 1 commit intoRIOT-OS:masterfrom
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cpu/stm32u5: Fix LSI initialization#22239
flxmls wants to merge 1 commit intoRIOT-OS:masterfrom
flxmls:patch-1

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@flxmls
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@flxmls flxmls commented May 5, 2026

To enable the LSI oscillator on STM32U5, RCC_CSR was used instead of RCC_BDCR, which is the correct register.

Contribution description

After clearing the reset status flags, the program got stuck in the LSIRDY loop on the next restart. After checking the reference manual, I identified that the wrong register was being used. Once the register was corrected, the program ran as expected.

Testing procedure

I wrote a simple watchdog code where the watchdog triggers a reset.

Issues/PRs references

None

Declaration of AI-Tools / LLMs usage:

AI-Tools / LLMs that were used are:

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@flxmls flxmls requested review from aabadie and vincent-d as code owners May 5, 2026 06:15
@github-actions github-actions Bot added Platform: ARM Platform: This PR/issue effects ARM-based platforms Area: cpu Area: CPU/MCU ports labels May 5, 2026
@crasbe crasbe added Type: enhancement The issue suggests enhanceable parts / The PR enhances parts of the codebase / documentation CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels May 5, 2026
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riot-ci commented May 5, 2026

Murdock results

✔️ PASSED

c760407 Update stmclk_common.c

Success Failures Total Runtime
11108 0 11108 11m:19s

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@AnnsAnns
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AnnsAnns commented May 5, 2026

Hello, thank you for your PR, can you give more detailed testing procedures how one might properly - test this PR, the current description of the testing procedure sounds more like your expected result with this PR than how to replicate it properly. Thank you so much for your contribution!

@kfessel
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kfessel commented May 5, 2026

the old code was probably not tested

from the stm32u5 reference manual :

image

i think this confirms the change

@flxmls: please fix commit message and PR message

https://github.com/RIOT-OS/RIOT/blob/master/CONTRIBUTING.md#commit-conventions


note for future work:

instead of redfining bit names to old names and then write to the old register
we should check check the name of the appropriate macrons and the existing one define the register we write to

#if defined(RCC_BDCR_LSION)
RCC->BDCR |= RCC_BDCR_LSION;
while (!(RCC->BDCR & RCC_BDCR_LSIRDY)) {}
#elif  defined(RCC_CSR_LSION)
RCC->CSR |= RCC_CSR_LSION;
while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
#elif  defined(RCC_CSR2_LSION)
RCC->CSR2 |= RCC_CSR2_LSION;
while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
#else 
#warn "i got not clue where LSIon is for this CPU"
#endif

@kfessel kfessel changed the title Update stmclk_common.c cpu/stm32u5: Fix LSI initialsation May 5, 2026
cpu/stm32/stmclk: fix RCC register selection for STM32U5
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flxmls commented May 5, 2026

Thank you so much for your help. I've changed the commit message. I hope it's okay now.

@crasbe crasbe changed the title cpu/stm32u5: Fix LSI initialsation cpu/stm32u5: Fix LSI initialization May 5, 2026
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kfessel commented May 6, 2026

Thank you so much for your help. I've changed the commit message. I hope it's okay now.

seems like it is still the old message:

Update stmclk_common.c

did you push the correct branch? you did but see below

the title of this pr now gives a good hint how the title of the commit should look like -- the title hidden in your commit description is also good

--

ahh i see

Update stmclk_common.c

cpu/stm32/stmclk: fix RCC register selection for STM32U5

is your current commit message -> you need to remove the first line that title is OK

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Area: cpu Area: CPU/MCU ports CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: ARM Platform: This PR/issue effects ARM-based platforms Type: enhancement The issue suggests enhanceable parts / The PR enhances parts of the codebase / documentation

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5 participants