Open-source Python tooling for semiconductor CAD and EDA workflows.
This repository serves as the central index for a collection of focused, production-grade Python libraries built for engineers working in chip design, physical verification, and timing analysis. Each tool is maintained as a standalone package and can be installed independently via PyPI.
Robust parsers for industry-standard EDA file formats. Each library is designed for correctness, performance, and ease of integration into existing CAD flows.
| Package | Description | Status |
|---|---|---|
| sdf-parser | Parse Standard Delay Format (SDF) files for timing back-annotation and analysis |  |
| liberty-parser | Parse Liberty (.lib) timing and power characterization files |  |
| verilog-parser | Parse structural and behavioral Verilog netlists for downstream analysis |  |
Each package is available on PyPI and can be installed independently:
pip install sdf-parser
pip install liberty-parser
pip install verilog-parserfrom sdf_parser import SDFParser
parser = SDFParser("path/to/design.sdf")
delays = parser.parse()
for path in delays.timing_paths:
print(path.cell, path.rise_delay, path.fall_delay)These tools are built around a few core principles:
- Format fidelity — parsers follow the official specifications closely and handle real-world files from commercial EDA tools (Cadence, Synopsys, Mentor).
- Python-native — no external EDA tool dependencies. Pure Python with optional NumPy acceleration where relevant.
- Integration-first — designed to slot into existing CAD flows, CI pipelines, and characterization frameworks, not replace them.
- Well-documented — every package ships with a detailed README, sample files, and usage examples.
The following tools are under active development and will be published in the coming months:
hspice-utils— Parse and post-process HSPICE simulation output for characterization workflowspegasus-utils— Interface with Cadence Pegasus physical verification run data
These libraries are authored and maintained by Rohan, a semiconductor CAD engineer with extensive experience building Python tooling for chip design workflows — spanning timing analysis, cell characterization, physical verification, and ESD path resistance reporting.
With a background in the semiconductor industry and a strong focus on automation, Rohan builds tools that are practical, integration-friendly, and designed to work cleanly inside real production CAD flows rather than exist as academic exercises.
If you work in EDA and have feedback, encounter a bug, or are interested in consulting or collaboration, feel free to open an issue or connect on LinkedIn.
Contributions are welcome. Please open an issue before submitting a pull request so we can align on scope and approach. Each sub-package has its own CONTRIBUTING.md with package-specific guidelines.
All packages in this collection are released under the Apache License 2.0 unless otherwise noted in the individual package repository.