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Merged
fpistm merged 2 commits into from
Mar 12, 2026
+3,357 −1,505
Merged

chore(g4): update to latest STM32CubeG4 v1.6.2 #2925

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a49da9e
system(g4) update STM32G4xx HAL Drivers to v1.2.6
fpistm Mar 12, 2026
23693f7
system(g4): update STM32G4xx CMSIS Drivers to v1.2.6
fpistm Mar 12, 2026
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20 changes: 11 additions & 9 deletions system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g411xb.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2995,7 +2995,7 @@ typedef struct

/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
Expand All @@ -3004,6 +3004,8 @@ typedef struct
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */

/* Legacy defines */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */

#define DMAMUX_CxCR_SOIE_Pos (8U)
Expand Down Expand Up @@ -8008,8 +8010,8 @@ typedef struct
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk

/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
Expand Down Expand Up @@ -9997,27 +9999,27 @@ typedef struct

/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */

/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */

/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */

/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand All @@ -10031,7 +10033,7 @@ typedef struct

/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */

/******************* Bit definition for TIM_BDTR register *******************/
Expand Down
20 changes: 11 additions & 9 deletions system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g411xc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3083,7 +3083,7 @@ typedef struct

/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
Expand All @@ -3092,6 +3092,8 @@ typedef struct
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */

/* Legacy defines */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */

#define DMAMUX_CxCR_SOIE_Pos (8U)
Expand Down Expand Up @@ -8196,8 +8198,8 @@ typedef struct
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk

/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
Expand Down Expand Up @@ -10215,27 +10217,27 @@ typedef struct

/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */

/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */

/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */

/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand All @@ -10249,7 +10251,7 @@ typedef struct

/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */

/******************* Bit definition for TIM_BDTR register *******************/
Expand Down
20 changes: 11 additions & 9 deletions system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g414xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3448,7 +3448,7 @@ typedef struct {

/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
Expand All @@ -3457,6 +3457,8 @@ typedef struct {
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */

/* Legacy defines */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */

#define DMAMUX_CxCR_SOIE_Pos (8U)
Expand Down Expand Up @@ -12099,8 +12101,8 @@ typedef struct {
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk

/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
Expand Down Expand Up @@ -14233,27 +14235,27 @@ typedef struct {

/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */

/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */

/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */

/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand All @@ -14267,7 +14269,7 @@ typedef struct {

/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */

/******************* Bit definition for TIM_BDTR register *******************/
Expand Down
20 changes: 11 additions & 9 deletions system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3122,7 +3122,7 @@ typedef struct

/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
Expand All @@ -3131,6 +3131,8 @@ typedef struct
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */

/* Legacy defines */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */

#define DMAMUX_CxCR_SOIE_Pos (8U)
Expand Down Expand Up @@ -8210,8 +8212,8 @@ typedef struct
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk

/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
Expand Down Expand Up @@ -10539,27 +10541,27 @@ typedef struct

/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */

/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */

/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */

/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
Expand All @@ -10573,7 +10575,7 @@ typedef struct

/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */

/******************* Bit definition for TIM_BDTR register *******************/
Expand Down
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