Build your hardware, easily!

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

RISC-V XV6/Linux SoC, marchID: 0x2b

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

32-bit RISC-V microcontroller for embedded, FPGA and ASIC applications

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Basic RISC-V Test SoC

Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals

The Antikernel operating system project

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

System on Chip toolkit for Amaranth HDL

ElemRV - End-to-end Open-Source RISC-V Microcontroller

A Modeling and Verification Platform for SoCs using ILAs

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

Development platform for the Espressif ESP32 WiFi/Microcontroller SoC

Small Processing Unit 32: A compact RV32I CPU written in Verilog

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.